SCOTUS Denies Appeal Seeking to Clarify Federal Circuit’s ‘Why’ Requirement for Establishing Section 112(f) Equivalency

Today, the U.S. Supreme Court denied the petition for writ of certiorari filed in Genuine Enabling Technology LLC v. Sony Group Corp., which challenged lower court rulings dismissing Genuine Enabling Technology’s (GET) patent infringement claims against Sony Playstation controllers under the doctrine of equivalents. In denying cert, the Court avoided clarifying whether a patentee’s statutory presumption under 35 U.S.C. § 112(f) to equivalents of a means-plus-function claim can be extinguished as a matter of law for failing to account for each component of the claimed structure.

Odetics: Structure Components Corresponding to Claimed Function Aren’t Limitations

GET filed its cert petition in September following the Federal Circuit’s precedential decision this February affirming the District of Delaware’s summary judgment ruling of noninfringement for Sony as to U.S. Patent No. 6219730, which claims a user input apparatus with an encoding means for synchronizing input streams into a combined data stream. Claiming priority to a patent application filed in 1998, the ‘730 patent solved shortcomings of input devices, which required individual connections, by merging data from multiple peripherals into a single stream transmittable over one communication link.

GET sued Sony asserting claims of the ‘730 patent against Playstation gaming consoles and controllers, the latter of which transmits user button presses and accelerometer motion data over one Bluetooth link. GET’s expert witness testified that these two kinds of data streams were synchronized to a bit-rate clock in the same way as block 34, a framer component that synchronizes data streams disclosed in one embodiment of the ‘730 patent’s invention. After finding that GET’s expert omitted aspects of block 34, including the CODEC, data selector and sampling process, without asserting that they were insubstantial to the disclosure, the district court granted summary judgment. This ruling was affirmed by the Federal Circuit, which underscored that GET’s expert “offer[ed] no meaningful explanation of why the bit-rate clock is the only part of logic block 34 that matters.”

Although the CAFC’s ruling cited Odetics v. Storage Technology Corp. (1999) as precedent on structural equivalence, GET’s cert petition argued that the appellate court failed to follow its holding that “[t]he individual components… of an overall structure that corresponds to the claimed function are not claim limitations.” This follows the Supreme Court’s 1997 ruling in Warner-Jenkinson Co. v. Hilton Davis Chemical Co., which explained that the means of a Section 112(f) means-plus-function claim is the “element” for which “claim[s] shall be construed to cover… equivalents thereof.”

While the doctrine of equivalents arises in common law doctrine, the statutory language of Section 112(f) applies it in a restrictive manner that narrows the application of literal claim elements, GET’s petition noted. Patentees are responsible for satisfying the function-way-result test established by the Supreme Court’s 1950 Graver Tank & Manufacturing v. Linde Air Products ruling, and while Section 112(f) was enacted by Congress in response to a separate Court ruling invalidating a combination claim relying on functional language, GET contended that Graver Tank did not elicit a similar response. Not only did the Federal Circuit do away with Graver Tank’s standard for showing equivalency, GET argued that the decision below abolished that decision’s allocation of equivalency to the factfinder, and read interchangeability out of the function-way-result test.

Federal Circuit’s Demanding ‘Why’ Requirement Troublesome in Logic Design Context

Through both Lear Sigler v. Sealy Mattress Co. of Michigan (1989) and Malta v. Schulmerich Carillons (1992), the Federal Circuit developed an additional requirement that patentees explain why the function, way and result of the claimed equivalent are substantially the same as the patented invention. The extremely demanding form of the “why” requirement appealed by GET is particularly troublesome in the logic design context, where competitors have countless interchangeable implementations for avoiding infringement liability despite equivalent functions, the petition for cert explained. Establishing this requirement as a matter of law, the Federal Circuit has set aside several jury verdicts finding equivalency, including a $675 million damages award to VLSI in February 2023. GET argued that the Federal Circuit’s justification for its “why” requirement for limiting equivalency lacks force in the Section 112(f) means-plus-function context, where Congress has already limited the literal scope of the claim to the disclosed structure.

This “why” requirement was imported into the Section 112(f) analysis by the Federal Circuit’s 2021 ruling in Traxcell Technologies v. Sprint Communications, upon which the CAFC relied in finding that GET’s claimed equivalency failed. Traxcell’s outcome was defensible, GET argued, because of the detailed algorithm serving as the structure for the claimed means: “in an algorithm the steps are the way the overall structure achieves its result.” By contrast, components of a logic design can be rearranged or replaced by a skilled artisan without changing how the logic design’s structure functions. Although it acknowledged that Odetics establishes that Section 112(f) equivalency doesn’t require a component-by-component analysis, the CAFC required exactly that accounting, according to GET.

Despite several dissents to the Federal Circuit’s application of the “why” requirement from Circuit Judges Pauline Newman, Jimmie Reyna and Alan Lourie, the full CAFC refuses to revisit the rule. GET argued that it made an equivalency showing sufficient under Graver Tank: its expert testimony on the interchangeability of logic circuits performing the same operation was unrebutted; that testimony established that the disclosed and accused structures operate the same way by synchronizing data streams to a bit-rate clock; and limited the selection of relevant components by tracing signal paths serving as the function-performing core.